Embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a clock control circuit and a clock generation circuit including the same.
Synchronous memory devices refer to semiconductor memory devices which operate in synchronization with an external clock. Among the synchronous memory devices, a synchronous dynamic RAM (SDRAM) and a double data rate SDRAM (DDR SDRAM) are the mainstream in the markets of semiconductor memory devices.
A data input/output operation of an SDRAM is achieved by data access which is performed one time in synchronization with a rising edge of an external clock in each clock cycle. On the other hand, a data input/output operation of a DDR SDRAM is achieved by data access which is performed two times in each clock cycle. Each data access is performed in synchronization with rising and falling edges of an external clock through an internal circuit, called a delay locked loop (DLL) circuit.
As such, a data input/output operation of a synchronous memory device is performed in synchronization with an external clock. In the synchronous memory device, however, the data input/output operation synchronized with the external clock is practically performed even when a read or write operation is not performed, causing unnecessary current consumption.